Multi-channel digital clock

ABSTRACT

Multi-channel digital clock for aircrart in which clock pulses are generated at a predetermined rate and applied to three independently controlled counters to determine different times such as real or clock time, flight time and elapsed time. The outputs of the counters are applied to a digital display by means of logic gates, and the time to be displayed is selected by a small single pole switch and an additional gate. The counts are transferred to the display on a time sharing basis which substantially reduces the number of lines required for the purpose. Operating power is normally supplied to the clock from an external source, and a battery is provided for supplying power to low power circuits such as the pulse source and counters to keep them running in the absence of external power. Switch operated means is provided for doubling the rate of the pulses applied to the real time counter or interrupting the application of pulses whereby the counter can be set up or down. Reset signals are applied to the flight time counter through a logic gate which prevents this counter from being reset while the aircraft is in operation. The elapsed time counter can be started, stopped and reset as desired.

United States Patent [191 Torresdal [4 Nov. 11, 1975 [54] MULTI-CI-IANNEL DIGITAL CLOCK [76] Inventor: David N. Torresdal, 427 Hillcrest Way, Redwood City, Calif. 94062 [22] Filed: Oct. 10, 1973 [21] Appl. No.: 404,920

OTHER PUBLICATIONS Beuscher, Budlong, Haverty, Electronic Switching Theory and Circuits," Van Nostrand Reinhold Col., New York, 1971, p. 49.

Primary Eramt'ner.loseph W. Hartary Assistant E.\aminerU. Weldon Attorney, Agent, or FirmFlehr, Hohbach, Test, Albritton & Herbert 64 TIA 6 [57] ABSTRACT Multi-channel digital clock for aircrart in which clock pulses are generated at a predetermined rate and applied to three independently controlled counters to determine different times such as real or clock time, flight time and elapsed time. The outputs of the counters are applied to a digital display by means of logic gates, and the time to be displayed is selected by a small single pole switch and an additional gate. The counts are transferred to the display on a time sharing basis which substantially reduces the number of lines required for the purpose. Operating power is normally supplied to the clock from an external source, and a battery is provided for supplying power to low power circuits such as the pulse source and counters to keep them running in the absence of external power. Switch operated means is provided for doubling the rate of the pulses applied to the real time counter or interrupting the application of pulses whereby the counter can be set up or down. Reset signals are applied to the flight time counter through a logic gate which prevents this counter from being reset while the aircraft is in operation. The elapsed time counter can be started, stopped and reset as desired.

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LF'L FLI- DEC. 0121 DEC, Did Did 2ft particularly suitable for aircraft. 1 In the operation and control of aircraft, pilots need MULTI-CHANNEL DIGITAL CLOCK BACKGROUND. OF THE INVENTION A digital clock'intended to overcome some of the problems of conventional aircraft clocks is described in U.S. Pat. No.'3,646,75l. This clock includes three sep- .arate clock channels and a switch for selectively conii'ecting one of the channels to a digital display. The

number of lines which must be switched requires a relatively large switch, and the clock'is unsuitable for many aircraft.

SUMMARY AND OBJECTS OF THE INVENTION In the digital clock of the invention, clock pulses are generated at a predetermined rate and applied to three independently controlled counters to determine different times such as real or clock time, flighttime and elapsed time. The outputs of the counters are applied to a digital display by means of logic gates, and the time to be displayed is. selected by a small single pole switch and an additional gate; The counts are transferred to the display on a timesharing basis which substantially reduces the numberof lines. required for the purpose. Operating power is normally supplied to the clock from an external source, and abattery is provided'for supplying power to low power. circuits such as the pulse source and counters to keep them runningin the absence of external power. Switch operated means is provided for doubling the rate of the pulses applied to the real time counter or interrupting the application of .-p.u lses whereby the counter can be setup or down.

Reset signals are-applied to the flight time counter through a logic gate which prevents this counter from being reset while the aircraft is in operation. The elapsed time counter can be started, stopped and reset as desired.

It is in general an object of the invention to provide a newand improved multi-cha'nnel digital clock for aircraft.

,Another, object. is to provide a'digital clock of the BRIEF DESCRIPTION OF THE DRAWINGS FIG. I is a block diagramof one embodiment of a multi-channel digital clock according to the invention.

FIG.'2 is a block diagram of one of the digital counters of the embodiment shown in FIG. 1. I FIG. 3 is a circuit diagram of a gating network for ap plying the output of one of the counters to the digital display in the embodiment of FIG. I.

FIG. 4 is a block diagram of the digital display Litilized in the embodiment of FIG. 1.

FIG. 5 is a circuit diagram, partly in block form of a power supply for the embodiment shown in FIG. 1

DESCRIPTION OF THE PREFERRED EMBODIMENT.

As illustrated in FIG. 1, the clockincludes a soui' ce of clock pulses II, a first clock channel comprising a counter -12 and a gating network 13, a second clock channel comprising a counter 14 anda gating network 16, a third clock channel comprising a counter 17 and a gating network 18, and a digital display 19. As discussed more fully hereinafter, counters l2, l4 and 17 are arranged for counting real or clock time, flight time and elapsed time, respectively.

Pulse source '11 comprises an oscillator 21 which, in the preferred embodiment, is a crystal controlled oscillator operating at a frequency of 163.84 KHz. The output of oscillator 21 is connected to the-input of a 13 stage binary ripple counter 22 which divides the oscillator signal by 2 to provide an output at the rate of 20 pulsesper second (PPS). The 20 PPS signal from counter 22 is shaped by a NAND gate 23 in that whenever the signal from counter 22 is at or below thelow threshold level of the gate, the output of the gate is high,-and'whenever the signal from counter 22 is at or above the high'threshold level of the gate, the output' of the gate is low. The rectangular signal thus delivered by gate 23 is applied to the set inputs of J-K flip-flops 24 and 26. The flip-flops divide the pulse rate by 2, producing output pulses at a rate of 10 PPS.

The 10 PPS output of flip-flop 24 is normally applied to the input of counter 12 by NAND gates 28 and 29 In this regard, the output of the flip-flop is connected to one input of NAND gate'28, which normally receives an enabling signal at a second input, and the output of this gate is connected to one input of NAND gate 29. The second input of gate 29 is normally maintained at a high logic level by a resistor 31 connected to a suitable voltage source, such as +5 volts.

Means is provided for setting counter 12 up or down relative to the time of day by applying pulses to the counter at a rate higher than 10 PPS or by blocking the passage of pulses. This means includes a switch 32 and NAND gates 33 and 34 which cooperate with gates 28 and 29 for this purpose. One contact of switch 32 is connected to the second input of NAND gate 29, a second contact is connected to the inputs of NAND gate 33, and the movable contact is grounded. The switch has three positions, and the movable contact is preferably biased toward a neutral position in which it does not contact either of the other contacts. The inputs of gate' 33 are normally maintained at a high logic level by a resistor 36 connected to a suitable voltage source. The output of gate 33 is connected to the reset input of flipflop 24 and to one input of NAND gate 34. Pulses at the rate of 20 PPS are applied tothe second input of gate 34 from the output of pulse-shaping NAND gate 23. I

In normal operation of counter 12, switch 32 is in its neutral position, and pulses occurring at the rate of 10 PPS are applied to the counter from flip-flop 24 by NAND gates 28 and 29. When switch 32 is moved to its DOWN position. the second input of NAND gate 29 is made low, and no pulses can pass to the counter. With the switch in its UP position, flip-flop 24 is locked in its reset state, and gates 34 and 29 are conditioned to pass the PPS pulses from gate 23 to gate 28 and the counter. I

Flight time counter 14 receives clock pulses at the rate of 10 PPS from flip-flop 26 through a control gate 38. As illustrated, gate 38 is a NAND gate, and one input of this gate is connected to the output of flip-flop 26. The other input of gate 38 is connected to a circuit in the aircraft which is energized to provide a high logic level when the aircraft is in flight. This input can, for example, be connected to a light which is on when the landing gear' is raised or to an air switch which closes when the aircraft begins its takeoff run.

Means is provided for resetting flight time counter 14 to zerowhen the aircraft power is off. This means includes a NAND gate 41 having its inputs connected to the aircraft power system by a resistor 42. The output of gate 41 is connected to one input of a NAND gate 43, and the second input of gate 43 is connected to a voltage source by a resistor 44 and a normally open switch 46. The output of gate 43 is connected to the inputs of a NAND gate 47, and the output of this gate is connected to the reset input of counter 14. The counter is reset by a reset signal having a high logic level, and gate 47 inverts the output of gate 43 to provide such a signal if switch 46 is closed while the aircraft power is turned off. With the power on, the output of gate 41 is low, making the output of gate 43 high and the output of gate 47 low, whereby the counter cannot be reset.

Elapsed time counter 17 receives clock pulses at the rate of 10 PPS from flip-flop 26 through a control gate 49. As illustrated, this gate is a NAND gate, and one of its inputs is connected to the output of the flip-flop. The second input of this gate is normally maintained at a low logic level by a resistor 51 connected to ground. A switch 53 is provided for controlling the operation of counter 17, and this switch is preferably a single pole, three-position switch having its movable contactconnected to a suitable voltage source such as +5 volts. One fixed contact is connected to the second input of gate 49, and the other fixed contact is connected to the reset input of counter 17. With the switch in its neutral or OFF position, gate 49 is disabled and the counter is stopped. With the switch in its RUN position, gate 49 is enabled and clock pulses are delivered to the counter. The counter can be reset by moving the switch to its ZERO position, thereby applying +5 volts to the reset input of the counter.

As discussed more fully hereinafter, gating networks l3, l6 and 18 control the passage of signals from the counters to the display. The time to be displayed is determined by a selector switch 56 and a NAND gate 57 which supply output control signals to the gating networks. In the preferred embodiment, switch 56 is a single pole, three-position switch having one movable contact and two fixed contacts. The movable contactv is grounded, and the fixed contacts are connected to the output control inputs of gating networks 13 and 18. These inputs are normally maintained at a high level by resistors 58 and 59 connected to a source of 305 volts. The fixed switch contacts are connected to the inputs of NAND gate 57, and the output of this gate is connected to the output control input of gating network 16. A low level at the output control input of any one of the gating networks will condition the network to transfer the count from the associated counter to the display.

The signals are transferred from the counters to the display on a time sharing basis in which the digits are divided into two groups which are transferred alternatively over a single set of lines. The time sharing operation is controlled by a free running square wave generator 61 which, in the preferred embodiment, produces a square wave having a frequency of 600 Hz. This square wave is passed through inverters 62 and 63 to provide signals of opposite polarities which are applied to the display and to digit control inputs of the gating networks in a manner described hereinafter.

Counters l2, l4 and 17 are all similar in structure, and a preferred structure is illustrated in FIG. 2. Each counter comprises a plurality of binary counting stages for registering different digits of the count. Thus, as illustrated, the output of input control gate 29, 38 or 49 is connected to the input of a divide-by-IO counter 64, and the output of this counter is connected to the input of a second divide-by-10 counter 71. The output of counter 71 is connectedto the input of a divide-by-6 counter 72, and the output of this counter is connected to the input of a divide-by-IO counter 73. The output of counter 73 is connected to the input of a divide-by-6 counter 74, and the output of this counter is connected to the input of a divide-by-10 counter 75. The output of counter 75 is connected to the input of another counter 76 which, for 24-hour clock operation, is a divide-by-2.4 counter.. If 12-hour clock operation is desired, counter 76 can be a divide-by-L2 stage. When 10 pulses per second are applied to the input control gate, counter 64 counts tenths of seconds, counter 71 counts seconds, counter 72 counts tens of seconds, counter 73 counts minutes, counter 74 counts tens of minutes, counter 75 counts hours, and counter 76 counts tens of hours.

Means is provided for advancing clock counter 12 an hour at a time, as might, for example, be desirable when the aircraft travels from one time zone to another. This means includes a normally open switch 81, one contact of which is connected to +5 volts, the other contact being connected to a voltage divider comprising resistors 82 and 83. A capacitor 84 is connected across resistor 83, and the junction of the resistors is connected to counting stage 75 of counter 12. Closing switch 81 causes a pulse to be applied directly to this stage, advancing the count in the counter by one hour.

In the preferred embodiment, 6 digits are displayed, and the information for these 6 digits is provided by counting stages 71-76 in BCD form on output lines designated by the reference numerals of the stages and the letters A, B, C and D. For example, line A71 designates the 2 output of counting stage 71, and line C72 designates the 2 output of stage 72. A total of 20 output lines are required for a six-digit, 24-hour clock, and a three-channel clock has such lines.

In order to reduce the number of lines involved, the digits are arranged in two groups which are transferred to the display during alternate half cycles of the control signal from square .wave generator 61. Thus, during one half cycle, the counts from counting stages 76, and 73 are transferred, and the first, second and fourth digits are displayed. During the next half cycle, the counts from counting stages 74, 72 and 71 are transferred, and the third, fifth and sixth digits are displayed. With a control signal having a frequency of-600 Hz, the duration of each half cycle is 1/1200 second, and the absence of a portion of the digits for this short time is not perceptible to the human eye.

The details of gating networks 13, 16 and 18 are shown in FIG. 3, and since the networks are similar, only one is shown. The digit control signal from square wave generator 61 and inverter 63 is applied to the input of an inverter 86, and the output of this inverter is connected to the input of another inverter 87. The outputs of inverters 86 and 87 are connected, respectively, to digit control lines 88 and 89. The output control signal from switch 56 or NAND gate 57 is applied to an output control line by inverters 92 and 93.

The gating network includes AND gates 101-120 which are arranged in pairs, with one input of the oddnumbered gate in each pair connected to digit control line 88 and one input of the even-numbered gate in each pair connected to digit control line 89. Thus, the

gates in each pair receive high or enabling signals during alternate halves of the cycle of the signal from generator 61.

AND gates 101-120 have second inputs which are connected to the output lines of the counter with which the particular gating network is associated. The output lines which carry the data for the first, second and fourth digits are connected to gates which are controlled by control line 89, and the output lines carrying data for the third, fifth and sixth digits are connected to gates which are controlled by control line 88. Thus, the information for the first, second and fourth digits is passed when control line 89 is high, and the information for the third, fifth and sixth digits is passed when control line 88 is high.

The outputs of AND gates 101-120 are connected to the inputs of NOR gates 121-130, with the two AND gates in each pair being connected to the same NOR gate. A third input of each NOR gate is connected to output control line 91, and the signals from the AND gates pass through the NOR gates only when the particular clock channel is selected and this line is low. The outputs of NOR gates 121-130 are applied to data lines 131-140 by transistors 141-150 which are turned off, presenting a high output impedance, in the absence of signals from the NOR gates.

At this point, it can be noted that the number of data lines has been reduced from 20 at the output of the counter at at the output of the gating network.

As illustrated in FIG. 4, display 19 includes sevensegment display elements 151-156 and decoder/drivers 161-166. The inputs of the decoders are connected to data lines 131-140, and the outputs of the decoders are connected to the inputs of the display elements. The display elements and decoders are arranged in two groups corresponding to the two groups of counting stages, and data lines 131-140 are each connected to one decoder in each group. Thus, for example, data line 140, which carries data for the first and third digits, is connected to the A or 2 inputs of decoders 166 and 164.

The output of inverter 62 is connected to a digit control line 168 which is connected to the control inputs of decoders 164, 162 and 161. When the signal on this line is high, the data for the third, fifthand sixth digits is transferred to the display elements, and these digits are displayed. The output of inverterr 63 is connected to a digit control line 169 which in turn is connected to the control inputs of decoders 166, and 163. When the signal on line 169 is high, the data for the first. second and fourth digits is transferred to the display elements, and this group of digits is displayed.

In the preferred embodiment. decoder/drivers 161-166 are Texas Instruments type SN7447 decoders which have internal pull-up resistors. These resistors maintain the inputs at high logic levels unless they are pulled down by input signals. Output transistors 141-150 in the gating networks for the channels not selected for display at any given time are turned off and have high output impedences. Consequently, these channels have no effect on the display even though they are connected to the decoders.

Means is provided for supplying operating power to the clock from an external source such as the power available in an aircraft. This means includes a power supply regulator 171 having input terminals 172 and 173 for connection to a suitable source such as 14 VDC, and it delivers an output voltage on the order of +8 volts. The output of the power supply is connected to an output terminal 174 by a series of diodes 176-179 which reduce the output voltage from 8 volts to 5 volts. A Zener diode 180 and a capacitor 182 arre connected between output terminal 174 and ground. The Zener diode provides a reference voltage which is applied to the regulator by a voltage divider consisting of resistors 181a and 181b. Resistor 18112 is adjusted to provide an output voltage of 5 volts at terminal 174.

A 5.4 volt battery 183 is provided for powering certain portions of the clock to keep the clock alive in the absence of external power. The battery is connected to a second output terminal 184 by a diode 186. When external power is available, power from power supply 171 is also delivered to output terminal 184 by a diode 187 which is connected from the junction of diodes 178 and 179 to terminal 184. The pulse source, counters and other circuits with relatively low current requirements receive operating power from terminal 184, whereas the display and other circuits with relatively high current requirements receive operating power from terminal 174. In the absence of external power, the pulse generator and counters are operated from the battery and the display is not energized.

Anode voltage +V for display elements 151-156 is provided at an output terminal 188. Means is provided for switching this voltage between 8 and 5 volt levels to provide bright and dim displays, respectively. A diode 189 is connected between output terminals 174 and 188, and terminal 188 is also connected to the collector of a PNP transistor 191. The emitter of the transistor is connected to the +8V output of power supply 171, and a resistor, 192 connected between the base and emitter biases the transistor in an OFF condition. The state of transistor 191 is controlled by a switch 193 having one contact connected to a source of +5 volts and a second contact connected to the base of an NPN transistor 194. The emitter of transistor 194 is grounded, and this transistor is biased in an OFF condition by a resistor 196 connected between the base and ground. The collector of transistor 194 is connected to the base of transistor 191 by a resistorr 197. When switch 193 is in its BRIGHT position, transistors 194 and 191 are turned on, and 8 volts is supplied to output terminal 188 through transistor 191. When the switch is in its DIM position, both transistors are turned off, and volts is delivered to the outpt terminal through diode I89.

Operation and use of the clock can now be described. With switch 32 in the neutral position, as illustrated, counter 12 operates normally to count the time of day. This time can be displayed by placing selector switch 56 in the CLOCK position, thereby conditioning gating network 13 to deliver the count from counter 12 to display 19. The count is delivered'on lines 131-140 on a time sharing basis whereby the data for the first, second and fourth digits is passed and displayed during one half of the cycle of a control signal from square wave generator 61, and the data for the remaining digits is passed and displayed during the next half cycleQThe time sharing occurs at such a rapid rate that the display appears constant to the human eye.

Counter 12 can be set up or down at a rate of 1 second per second by means of switch 32. Placing the switch in its DOWN position disables NAND gate 29, blocking the passage of clock pulses to thecounter. Placing the switch in its UP position causes the counter to receive pulses at a rate of PPS, rather than the normal 10PPS rate. Counter 12 can also be advanced an hourat a time by closing switch 81 to apply a pulse directly to stage 75 in which hours are counted.

Flight time counter 14 is adapted to operate whenever anaircraft in which the clock is utilized is in flight.

If the control input of gate 38 is connected to the air switch of the aircraft, this switch will close and the count will begin when the aircraft starts its takeoff run.

The count will continue until the air switch is opened again, e.g. when the aircraft has landed.

The flight time counter can be reset to zero only when the aircraft power is turned off. With the power off, closing switch 46 causes a reset signal to be applied to the counter through gates 43 and 47. If the aircraft power is still on when the switch is closed, gate 41 will inhibit the passage of the reset signal through gate 43, and the closing of the switch will have no effect.

The flight time can be displayed by placing switch 56 in the FLIGHT TIME position, whereupon gate 57 will condition gating network 16 to deliver the count from counter 14 to the display. As with counter 12, the data from counter 14 is transferred on lines 131-140 and displayed on a time sharing basis.

Elapsed time counter 17 can be used to time any desired event such as a landing approach. The operation of this counter is controlled by gate 49 and switch 53. With the switch in the OFF position, the gate is disabled, blocking the passage of clock pulses to the counter. With the switch in the RUN position, pulses pass through gate 49, and the counter advances. This counter can be reset at any time desired by moving switch 53 to the ZERO position. The elapsed time can be displayed by placing selector switch 56 in the ELAPSED TIME position, thereby conditioning gating network 18 to deliver the count from counter 17 to the display. As with the other counters, the count is transferred and displayed on a time sharing basis.

When the time to be displayed is selected by switch 56, control line 91 in the gating network for the channel selected is at a low logic level, enabling the data signals for this channel to pass through the NOR gates and transistors to data lines 131-140. In the non-selected channels, control lines 91 are high, making the outputs of the NOR gates low and maintaining the transistors in their OFF condition.

The transfer of the data and the display of the digits on a time sharing basis is controlled by the 600 Hz square wave produced by generator 6l. During the half cycles when this signal is high, the outputs of inverters 63 and 87 are also high, making digit control lines 89 and 169 high. When line 89 is high. the data for the first, second and fourth digits passes through the evennumbered AND gates and is delivered to the decoders on lines 131-140. With the control lines 169 high, the data on lines 131-140 is decoded by decoders 166, 165 and 163 and applied to display elements 156, 155 and 153 to display the first, second and fourth digits, respectively.

During the half cycles when the square wave from generator 61 is low, the outputs of inverters 62 and 86 are high, making control lines 88 and 168 high. When control line 88 is high, data for the third, fifth and sixth digits passes through the odd-numbered AND gates and is delivered on lines 131-140 to the decoders. With control line 168 high, decoders 164, 162 and 161 decode the data on lines 131-140 and transfer the decoded data to display elements 154, 152 and 151 to display the third, fifth and sixth digits, respectively.

When the clock is used in an aircraft, operating power is obtained from the aircraft by power supply 171. In the absence of aircraft power or other external power, battery 183 supplies operating power to the pulse source and counters to keep the clock alive even though the display is turned off. When full power is restored, the correct time will be displayed. For daytime flights switch 193 is generally kept in its BRIGHT position, and 8 volts is applied to the display elements. At night the switch can be moved to its DIM position to reduce the display voltage to 5 volts and provide a softer display. 9

The invention has a number of important features and'advantages. It provides a multi-channel digital clock in which the time to be displayed is selected without cumbersome switches. Utilizing integrated circuit techniques, it can be constructed as a small unit which can be mounted in a standard 2%-inch aircraft clock mount.

It is apparent from the foregoing that a new and improved multi-channel digital clock has been provided. While only the presently preferred embodiment has been described, as will be apparent to those familiar with the art, certain changes and modifications can be made without departing from the scope of the invention as defined by the following claims.

I claim:

1. In a digital clock, a source of clock pulses occurring at a predetermined rate, digital display means comprising a plurality of digital display elements arranged in first and second groups, a plurality of digital counters, means for applying the clock pulses to the counters whereby each counter can advance independently of other counters to provide a count corresponding to the length of time the clock pulses are applied to that counter, each of the counters comprising a plurality of counting stages for registering different digits of the count in the counter, the stages in each counter being arranged in first and second groups corresponding to the groups of display elements, means for providing a cyclical control signal, manually controlled means for providing counter selection signals representative of one of the counters whereby one of thecounters is selected for display of the count therein, gating means connected to said counters, said gating means being responsive to the control signal and to the counter selection signals for applying the counts from the first and second groups of stages in the selected one of the counters to the display means during first and second portions of the cycle of thecontrolsignal, respectively, means responsive to the control signal for conditioning the first and second groups of display elements to display the counts applied to the display means during the first and second portions of the control signal cycle, respectively,, means for supplying operating power to the clock from an external source, a battery, and means for supplying operating power from the battery to a portion ofthe clock including the pulse source and at least one of the counters and excluding the display elements in the absence of power from the external source whereby said counter continues to operate notwit'hstanding the absence of external power v "2. A digital clock as in claim 1 further including switch operatedmeans for generating a reset signal and additional gating means responsive to" an externally provided enabling signal for applying the reset signal to one of the counters when the enabling signal is applied to the additional gating means and inhibiting the application of the reset signal to the counter in the absence of the enabling signal.

3. A digital clock as in claim 1 further including switch controlled means connected to one of the counters for applying pulses to said counter at a rate greater than the normal rate of the clock pulses whereby said counter can be advanced at a rate greater than the normal rate.

4. In a digital clock, a source of clock pulses occurring at a predetermined rate, a plurality of digital counters, means for applying the clock pulses to the counters whereby each counter can advance independently of other counters to provide a count corresponding to the length of time the clock pulses are applied to that counter, digital display means, manually operated counter selection means for providing counter selection signals corresponding to selected ones of the counters, gating means connected to the counters and to the display means and responsive to the counter selection signals for selectively applying the count from a selected one of the counters to the display means whereby the time represented by the count in the selected counter is displayed, means for supplying operating power to the clock from an external source, a battery, and means for supplying operating power from the battery to a portion of the clock including the pulse source and at least one of the counters and excluding the said display means in the absence of power from the external source whereby said counter continues to operate notwithstanding the absence of external power.

5. A digital clock as in claim 4 wherein each of the counters includes a plurality of counting stages for reg- .istering different digits of the count in the counter, the

stages in each counter being arranged in two groups, and the display means includes display elements for displaying the digits of the count, the display elements being arranged in two groups corresponding to the groups of counting stages, together with a single set of output lines interconnecting the gating means and the display elements and means for conditioning the gating means to apply 'the counts from the two groups of being applied to the other group of display elements during a second portion of the cycle of the control signal.

7. A digital clock as in'cla im'4 further including switch'controlled means connected toone of the count ers for'applying pulses to said counter at a'rate greater than the normal rate of the clock pulses whereby said counter can beadvanced at a rate greater than the nor s. A digital dock as in claim 4 further including switch operated means for generating a reset signal and gating means for applying thercst signal toone of the counters when an enabling signal is applied to said gat ing means and inhibiting the applicationof the reset signaltdthe counter in the absence of the 'en'abling signal.

9. In a digital clock, a source of clock pulses occurring at a predetermined rate, digital display means comprising a plurality of digital display elements arranged in first and second groups, a plurality of digital counters, means for applying the clock pulses to the counters whereby each counter can advance independently of other counters to provide a count corresponding to the length of time the clock pulses are applied to that counter, each of the counters comprising a plurality of counting stages for registering different digits of the count in the counter, the stages in each counter being arranged in first and second groups corresponding to the groups of display elements, means for providing a cyclical control signal, manually controlled means for providing counter selection signals representative of one of thecounters whereby one of the counters is selected for display of the count therein, gating means connected to said counters, said gating means being responsive to the control signal and to the counter selection signals for applying the counts from the first and second groups of stages in the selected one of the counters to the display means during first and second portions of the cycle of the control signal, respectively, means responsive to the control signal for conditioning the first and second groups of display elements to display the counts applied to the display means during the first and second portions of the control signal cycle, respectively, the means for providing counter selection signals comprising a manually operable switch for delivering first and second counter selection signals to said gating means when in first and second positions, respectively, and additional gating means connected to the switch and to the first named gating means and responsive to the first and second counter selection signals for delivering a third counter selection signal to the first named gating means when neither the first nor the second counter selection signal is present.

10. A digital clock as in claim 9 further including switch operated means for generating a reset signal and third gating means responsive to an externally provided enabling signal for applying the reset signal to one of the counters when the enabling signal is applied to said third gating means and inhibiting the application ofthe reset signal to the counter in the absence of the enabling signal. a

11. A digital clock as in claim 9 further including switch controlled means connected to one of the counters for applying pulses to said counter at a rate greater thanthe normal rate of the clock pulses whereby said counter can be advanced at a rate greater than the normal rate.

12. In a digital clock, a source of clock pulses occurring at a predetermined rate, a plurality of digital counters, means for applying the clock pulses to the counters whereby each counter can advance independently of other counters to provide a count corresponding to the length of time the clock pulses are applied to that counter, digital display means, manually operated counter selection means for providing counter selection signals corresponding to selected ones of the counters, gating means connected to the counters and to the display means and responsive to the counter selection signals for selectively applying the count from a selected one of the counters to the display means whereby the time represented. by the count in the one counter is displayed, the manually operated counter selection means comprising switch means for selectively applying first and second counter selection signals to the gating means connected to two ofthe counters and second gating means connected to the switch means and to the gating means connected to a third counter for applying a third counter selection signal to the gating means connected to the third counter when neither the first nor the second counter selection signal is presem.

13. A digital clock as in claim 12 further including switch controlled means connected to one ofthe counters for applying pulses to said counter at a rate greater than the normal rate of the clock pulses whereby said counter can be advanced at a rate greater than the normal rate.

14. A digital clock as in claim 12 further including switch operated means for generating a reset signal and third gating means responsive to an externally applied enabling signal for applying the reset signal to one of the counters when the enabling signal is applied to said additional gating means and inhibiting the application of the reset signal to the counter in the absence of the enabling signal. 

1. In a digital clock, a source of clock pulses occurring at a predetermined rate, digital display means comprising a plurality of digital display elements arranged in first and second groups, a plurality of digital counters, means for applying the clock pulses to the counters whereby each counter can advance independently of other counters to provide a count corresponding to the length of time the clock pulses are applied to that counter, each of the counters comprising a plurality of counting stages for registering different digits of the count in the counter, the stages in each counter being arranged in first and second groups corresponding to the groups of display elements, means for providing a cyclical control signal, manually controlled means for providing counter selection signals representative of one of the counters whereby one of the counters is selected for display of the count therein, gating means connected to said counters, said gating means being responsive to the control signal and to the counter selection signals for applying the counts from the first and second groups of stages in the selected one of the counters to the display means during first and second portions of the cycle of the control signal, respectively, means responsive to the control signal for conditioning the first and second groups of display elements to display the counts applied to the display means during the first and second portions of the control signal cycle, respectively, means for supplying operating power to the clock from an external source, a battery, and means for supplying operating power from the battery to a portion of the clock including the pulse source and at least one of the counters and excluding the display elements in the absence of power from the external source whereby said counter continues to operate notwithstanding the absence of external power.
 2. A digital clock as in claim 1 further including switch operated means for generating a reset signal and additional gating means responsive to an externally provided enabling signal for applying the reset signal to one of the counters when the enabling signal is applied to the additional gating means and inhibiting the application of the reset signal to the counter in the absence of the enabling signal.
 3. A digital clock as in claim 1 further including switch controlled means connected to one of the counters for applying pulses to said counter at a rate greater than the normal rate of the clock pulses whereby said counter can be advanced at a rate greater than the normal rate.
 4. In a digital clock, a source of clock pulses occurring at a predetermined rate, a plurality of digital counters, means for applying the clock pulses to the counters whereby each counter can advance independently of other counters to provide a count corresponding to the length of time the clock pulses are applied to that counter, digital display means, manually operated counter selection means for providing counter selection signals corresponding to selected ones of the counters, gating means connected to the counters and to the display means and responsive to the counter selection signals for selectively applying the count from a selected one of the counters to the display means whereby the time represented by the count in the selected counter is displayed, means for supplying operating power to the clock from an external source, a battery, and means for supplying operating power from the battery to a portion of the clock including the pulse source and at least one of the counters and excluding the said display means in the absence of power from the external source whereby said counter continues to operate notwithstanding the absence of external power.
 5. A digital clock as in claim 4 wherein each of the counters includes a plurality of counting stages for registering different digits of the count in the counter, the stages in each counter being arranged in two groups, and the display means includes display elements for displaying the digits of the count, the display elements being arranged in two groups corresponding to the groups of counting stages, together with a single set of output lines interconnecting the gating means and the display elements and means for conditioning the gating means to apply the counts from the two groups of counting stages to the corresponding groups of display elements over the single set of output lines on a time sharing basis.
 6. A digital clock as in claim 5 wherein the means for conditioning the gating means includes means for delivering a cyclical control signal to the gating means and display means, the counts from one group of stages being applied to the corresponding group of display elements during one portion of each cycle of the control signal and the counts from the other group of stages being applied to the other group of display elements during a second portion of the cycle of the control signal.
 7. A digital clock as in claim 4 further including switch controlled means connected to one of the counters for applying pulses to said counter at a rate greater than the normal rate of the clock pulses whereby said counter can be advanced at a rate greater than the normal rate.
 8. A digital clock as in claim 4 further including switch operated means for generating a reset signal and gating means for applying the rest signal to one of the counters when an enabling signal is applied to said gating means and inhibiting the application of the reset signal to the counter in the absence of the enabling signal.
 9. In a digital clock, a source of clock pulses occurring at a predetermined rate, digital display means comprising a plurality of digital display elements arranged in first and second groups, a plurality of digital counters, means for applying the clock pulses to the counters whereby each counter can advance independently of other counters to provide a count corresponding to the length of time the clock pulses are applied to that counter, each of the counters comprising a plurality of counting stages for registering different digits of the count in the counter, the stages in each counter being arranged in first and second groups corresponding to the groups of display elements, means for providing a cyclical control signal, manually controlled means for providing counter selection signals representative of one of the counters whereby one of the counters is selected for display of the count therein, gating means connected to said counters, said gating means being responsive to the Control signal and to the counter selection signals for applying the counts from the first and second groups of stages in the selected one of the counters to the display means during first and second portions of the cycle of the control signal, respectively, means responsive to the control signal for conditioning the first and second groups of display elements to display the counts applied to the display means during the first and second portions of the control signal cycle, respectively, the means for providing counter selection signals comprising a manually operable switch for delivering first and second counter selection signals to said gating means when in first and second positions, respectively, and additional gating means connected to the switch and to the first named gating means and responsive to the first and second counter selection signals for delivering a third counter selection signal to the first named gating means when neither the first nor the second counter selection signal is present.
 10. A digital clock as in claim 9 further including switch operated means for generating a reset signal and third gating means responsive to an externally provided enabling signal for applying the reset signal to one of the counters when the enabling signal is applied to said third gating means and inhibiting the application of the reset signal to the counter in the absence of the enabling signal.
 11. A digital clock as in claim 9 further including switch controlled means connected to one of the counters for applying pulses to said counter at a rate greater than the normal rate of the clock pulses whereby said counter can be advanced at a rate greater than the normal rate.
 12. In a digital clock, a source of clock pulses occurring at a predetermined rate, a plurality of digital counters, means for applying the clock pulses to the counters whereby each counter can advance independently of other counters to provide a count corresponding to the length of time the clock pulses are applied to that counter, digital display means, manually operated counter selection means for providing counter selection signals corresponding to selected ones of the counters, gating means connected to the counters and to the display means and responsive to the counter selection signals for selectively applying the count from a selected one of the counters to the display means whereby the time represented by the count in the one counter is displayed, the manually operated counter selection means comprising switch means for selectively applying first and second counter selection signals to the gating means connected to two of the counters and second gating means connected to the switch means and to the gating means connected to a third counter for applying a third counter selection signal to the gating means connected to the third counter when neither the first nor the second counter selection signal is present.
 13. A digital clock as in claim 12 further including switch controlled means connected to one of the counters for applying pulses to said counter at a rate greater than the normal rate of the clock pulses whereby said counter can be advanced at a rate greater than the normal rate.
 14. A digital clock as in claim 12 further including switch operated means for generating a reset signal and third gating means responsive to an externally applied enabling signal for applying the reset signal to one of the counters when the enabling signal is applied to said additional gating means and inhibiting the application of the reset signal to the counter in the absence of the enabling signal. 